This invention relates to systems for the non-destructive detection of damage or imperfections in insulative coatings on the surface of a semiconductor substrate. In particular, it relates to a test method and apparatus for determining defect density, location, and size in insulative coatings.
The manufacture of VLSI devices requires lithographic fabrication steps having characteristic features in the order of 1 micron or less. In order to achieve these exceptionally small dimensional tolerances, e-beam lithography together with deep UV resist techniques are necessary to provide both high sensitivity and high resolution. This is accomplished utilizing e-beam resists which are employed at a thickness over the substrate which approaches the smallest dimension of the exposed pattern. Such an exceptionally thin layer of resist is necessary since, at a given exposure dose, the thickness of the resist is a primary factor in determining its resolution.
In contrast to known contemporary processes which use a resist thickness in excess of 1.5 microns, future submicron process yields are highly dependent on resist defect levels. This dependency occurs due to a dramatic increase in defect density as a function of decreasing resist thickness. Moreover, the probability of device damage increases exponentially with increasing defect density. Therefore, it is apparent that final device yield is strongly related to resist defect levels. Given this requirement, users and manufacturers of resist in a submicron process have a standing requirement for a non-destructive test method of evaluating resist defect behavior. Users could employ such a test to diagnose process problems relating to defects without actually fabricating and testing devices. Resist manufacturers have a compatible need for such a test as a routine quality control technique.
Within the prior art, a variety of techniques are currently employed for evaluating defects in various resist coatings. One known quality control system relies on the transportation of defects into a thermal oxide film by wet etching. A second etching produces pits in the underlying silicon substrate. The etched pits are visually counted with the aid of a microscope in order to determine defect density. It has been established by empirical data and actual experience that this procedure is unsatisfactory for distinguishing high and low defect levels in various types of resist which are used for semiconductor lithography. The inability of this optical test process for judging resist quality is demonstrated by the fact that commonly one resist lot produces acceptable semiconductor yields while another resist lot produces very low yields yet, both upon optical evaluation, tested to have equivalent defect densities.
A more sensitive technique has been established to accurately distinguish defect densities in high and low defect resists of the type employed in optical quality control test systems. This more sensitive method involves transporting resist defects into a thermal oxide film by wet etching. This is followed by measuring dielectric breakdown voltage of the remaining oxide utilizing approximately 250 metal-oxide-semiconductor (MOS) capacitors fabricated on the wafer. The MOS technique realistically therefore reflects the effective defect density of a test resist since, device (capacitor) yield is actually measured. It is applicable to determine defects in the order of less than 1 .mu.m finding application in 500 .ANG. inorganic dielectrics. However, this test methodology does not provide information concerning defect size or other salient characteristics such as location. Such information is key in providing a complete envelope of defect yield data, vis-a-vis resist materials or process problems related to such defects.
A more significant deficiency of the MOS capacitor technique is that it requires access to the actual device manufacturing area since the test relies on availability of oxidation furnaces, clean process stations, metal evaporation, etc. Accordingly, while the MOS capacitor test is an excellent method for evaluating resist defects per se, it is logistically impractical for routine monitoring of resist quality.
Techniques of mapping semiconductor wafers in a non-destructive manner using chemical techniques are known in the prior art. In IBM TDB, Vol. 18, No. 12, May 1976, p. 4012, a system is described in which an array of light-emitting diodes is employed in order to illuminate different areas of the wafers so that cathodic current information is obtained on different segments of the wafer. The system described in IBM TDB, Vol. 18, No. 11, April 1976, p. 3623 utilizes a laser to scan the semiconductor material in order to map the depletion region. In this system, defect regions produce a decrease in current so that a map of semiconductor quality can be obtained. A determination of actual pinhole size is not made using these techniques.
Another technique of nondestructive testing of semiconductor articles is described in U.S. Pat. No. 4,125,440 wherein the semiconductor substrate is immersed in electrolyte solution which is held on a test stand by means of a vacuum holder. The surface is uniformly illuminated at a light density in the range of 50-75 foot candles and the substrate is negatively biased with respect to the electrolyte at a voltage level in the range of 50-65 volts. This produces hydrogen gas bubbles at electrically active damage sites indicative of defect density per se. Thus, this prior art technique also maps but does not actually measure pinhold-type defects.
Other prior art of less significance utilizing electrolytic cells for determining the integrity of semiconductor materials are disclosed in U.S. Pat. Nos. 2,805,347; 3,628,017; 3,755,026; 4,028,207; and 4,188,267. These various techniques relate to test systems for determining pinhole locations or density and do not provide comprehensive data concerning pinhole density pinhole location and pinhole size in a single test.
The application of a defect detector for use in insulative coatings employing an electrolyte system for purposes of mapping, that is, to outline a distribution of defects in addition to determining pinhole size, is disclosed in IBM TDB, Vol. 20, No. 1, June 1977, pp. 432-433. As disclosed therein, defects in an insulative layer on a silicon wafer are detected by determining current-voltage characteristics of a signal which is applied across the insulative layer and its substrate utilizing a platinum electrode immersed in a NaCl solution together with an electrical contacting pin contacting the substrate. The pinholes themselves are rendered visible, vis-a-vis a plating effect which decorates the defects when, if NaCl is used as the electrolyte, a white film outlines the defect or distribution thereof optical evaluation follows.
A technique for measuring the thickness of a dielectric layer on a conductive substrate is disclosed in U.S. Pat. No. 3,975,681 utilizing an electrode pair wherein an electrode is placed in a tube with one electrode having a capillary opening contacting the surface of the dielectric layer whose thickness is to be measured. The circuit is complete by utilizing this conductive substrate as the anode such that the thickness of the dielectric is measured as a function of the highest applied voltage which does not produce an increase in current flow in the system. Such a technique, however, is not readily applicable for a determination of defect densities and sizes.
Other prior art considered to be less significant than that discussed herein, vis-a-vis the present invention, comprises technology directed to other electrolytic techniques for measuring semiconductor imperfections as typified by U.S. Pat. Nos. 3,129,148; 3,366,554; 3,379,625; 3,384,556; 3,408,270; and 3,366,040. Finally, other electrolytic techniques for the manufacture of semiconductor components but not specifically directed to measuring and testing systems per se that have been considered are typified by U.S. Pat. Nos. 3,265,599; 3,267,014; 3,738,917; and 3,890,215.
A hallmark deficiency of the prior art is that it does not provide comprehensive data for determining the number, size, and location of pinhole defects in very thin insulator coatings. Various optical mapping techniques are either time-consuming and/or destructive and therefore incapable of precisely locating pinhole defects in the surface of such coatings. Other techniques, while providing the necessary sensitivity, do not afford turn-around time commensurate with processing requirements. Still other techniques, primarily chemical, do not provide the necessary sensitivity for use over a broad range of insulative coating applications, such as resist or other inorganic films typified by SiO.sub.2, quartz, Si.sub.3 O.sub.4 and various polymer coatings. Other known techniques, such as bubble trail, liquid crystal techniques and the like, suffer from the same disadvantages of the prior art discussed herein.